119 search results - page 16 / 24 » Static Energy Reduction Techniques for Microprocessor Caches |
IEEEPACT
2003
IEEE
14 years 27 days ago
2003
IEEE
We present a technique for reducing the power dissipation in the course of writebacks and committments in a datapath that uses a dedicated architectural register file (ARF) to hol...
DATE
2010
IEEE
14 years 21 days ago
2010
IEEE
—This paper presents a design space exploration of a selective load value prediction scheme suitable for energyaware Simultaneous Multi-Threaded (SMT) architectures. A load value...
MICRO
2002
IEEE
14 years 15 days ago
2002
IEEE
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
ARCS
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. ...
CF
2004
ACM
14 years 1 months ago
2004
ACM
Next generation architectures will require innovative solutions to reduce energy consumption. One of the trends we expect is more extensive utilization of compiler information dir...