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EMSOFT
2007
Springer
14 years 3 months ago
WCET estimation for executables in the presence of data caches
This paper describes techniques to estimate the worst case execution time of executable code on architectures with data caches. The underlying mechanism is Abstract Interpretation...
Rathijit Sen, Y. N. Srikant
ISLPED
2005
ACM
109views Hardware» more  ISLPED 2005»
14 years 2 months ago
Power reduction by varying sampling rate
The rate at which a digital signal processing (DSP) system operates depends on the highest frequency component in the input signal. DSP applications must sample their inputs at a ...
William R. Dieter, Srabosti Datta, Wong Key Kai
ICSE
1994
IEEE-ACM
14 years 1 months ago
TestTube: A System for Selective Regression Testing
This paper describes a system called TESTTUBE that combines static and dynamic analysis to perform selective retesting of software systems written in C. TESTTUBEfirst identifies w...
Yih-Farn Chen, David S. Rosenblum, Kiem-Phong Vo
IESS
2007
Springer
92views Hardware» more  IESS 2007»
14 years 3 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
14 years 1 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...