328 search results - page 62 / 66 » Static performance prediction of skeletal parallel programs |
HPCA
2001
IEEE
14 years 7 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
ICS
2005
Tsinghua U.
14 years 26 days ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
ASPLOS
1994
ACM
13 years 11 months ago
1994
ACM
Synchronization algorithms that are efficient across a wide range of applications and operating conditions are hard to design because their performance depends on unpredictable ru...
IEEEPACT
2005
IEEE
14 years 29 days ago
2005
IEEE
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...