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» Static timing analysis for modeling QoS in networks-on-chip
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KBSE
1998
IEEE
13 years 12 months ago
Automated Integrative Analysis of State-based Requirements
Statically analyzing requirements specifications to assure that they possess desirable properties is an important activity in any rigorous software development project. The analys...
Barbara J. Czerny, Mats Per Erik Heimdahl
IESS
2007
Springer
92views Hardware» more  IESS 2007»
14 years 1 months ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer
ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
14 years 1 months ago
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
Bao Liu
KDD
2009
ACM
166views Data Mining» more  KDD 2009»
14 years 8 months ago
Measuring the effects of preprocessing decisions and network forces in dynamic network analysis
Social networks have become a major focus of research in recent years, initially directed towards static networks but increasingly, towards dynamic ones. In this paper, we investi...
Jerry Scripps, Pang-Ning Tan, Abdol-Hossein Esfaha...
JCSS
2007
63views more  JCSS 2007»
13 years 7 months ago
Holistic analysis of asynchronous real-time transactions with earliest deadline scheduling
In distributed real-time systems, an application is often modeled as a set of real-time transactions, where each transaction is a chain of precedence-constrained tasks. Each task ...
Rodolfo Pellizzoni, Giuseppe Lipari