34 search results - page 5 / 7 » Statistical Analysis of Capacitance Coupling Effects on Dela... |
VTS
2000
IEEE
14 years 1 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
ICCAD
1998
IEEE
14 years 1 months ago
1998
IEEE
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
ASPDAC
2008
ACM
13 years 11 months ago
2008
ACM
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriv...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
3DIC
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...