306 search results - page 10 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ISPD
2012
ACM
12 years 2 months ago
2012
ACM
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents a versatile scheduling model and an efficient control synthesis methodology which enables architectural (high-level) design/synthesis systems to seamlessly su...
AUTOMATICA
2004
13 years 7 months ago
2004
This paper deals with feedback controller synthesis for timed event graphs in dioids, where the number of initial tokens and time delays are only known to belong to intervals. We ...
ITC
2003
IEEE
14 years 18 days ago
2003
IEEE
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
ICCAD
1992
IEEE
13 years 11 months ago
1992
IEEE
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...