306 search results - page 17 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ASPDAC
2009
ACM
14 years 2 months ago
2009
ACM
— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, wo...
TVCG
2012
11 years 10 months ago
2012
—In recent years, data-driven speech animation approaches have achieved significant successes in terms of animation quality. However, how to automatically evaluate the realism o...
GLVLSI
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
DAC
2012
ACM
11 years 10 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...