306 search results - page 40 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
DAC
1996
ACM
14 years 1 months ago
1996
ACM
CAD tool interoperability issues are a recurring impediment to constructing a design methodology, especially if the methodology incorporates point tools from several vendors. Failu...
TCAD
2008
13 years 9 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
TKDE
2011
13 years 4 months ago
2011
—It is essential to process real-time data service requests such as stock quotes and trade transactions in a timely manner using fresh data, which represent the current real worl...
RSP
2005
IEEE
14 years 3 months ago
2005
IEEE
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
ISORC
2009
IEEE
14 years 4 months ago
2009
IEEE
Distributed real-time automotive embedded systems have to be highly dependable as well as cost-efficient due to the large number of manufactured units. To close the gap between r...