306 search results - page 42 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
DAC
2004
ACM
14 years 4 days ago
2004
ACM
The performance of timing-driven placement methods depends strongly on the choice of the net model. In this paper a more precise net model is presented that does not increase nume...
POPL
2005
ACM
14 years 8 months ago
2005
ACM
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
SAC
2006
ACM
14 years 2 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
DAC
1994
ACM
14 years 15 days ago
1994
ACM
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
ISSS
2002
IEEE
14 years 1 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...