306 search results - page 47 / 62 » Statistical Delay Modeling in Logic Design and Synthesis |
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
ICCD
2007
IEEE
14 years 5 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
FMICS
2006
Springer
14 years 2 days ago
2006
Springer
Abstract. The design flow of systems-on-a-chip (SoCs) identifies several abstraction levels higher than the Register-Transfer-Level that constitutes the input of the synthesis tool...
ISLPED
2000
ACM
14 years 23 days ago
2000
ACM
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
As timing requirements in today’s advanced VLSI designs become more aggressive, the need for automated tools to diagnose timing failures increases. This work presents two such a...