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» Statistical Delay Modeling in Logic Design and Synthesis
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ISPASS
2009
IEEE
14 years 2 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
ICCAD
2003
IEEE
140views Hardware» more  ICCAD 2003»
14 years 4 months ago
Block-based Static Timing Analysis with Uncertainty
Static timing analysis is a critical step in design of any digital integrated circuit. Technology and design trends have led to significant increase in environmental and process v...
Anirudh Devgan, Chandramouli V. Kashyap
KDD
2008
ACM
174views Data Mining» more  KDD 2008»
14 years 7 months ago
Automatic identification of quasi-experimental designs for discovering causal knowledge
Researchers in the social and behavioral sciences routinely rely on quasi-experimental designs to discover knowledge from large databases. Quasi-experimental designs (QEDs) exploi...
David D. Jensen, Andrew S. Fast, Brian J. Taylor, ...
DAC
2004
ACM
14 years 23 days ago
Parametric yield estimation considering leakage variability
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inver...
Rajeev R. Rao, Anirudh Devgan, David Blaauw, Denni...
CASES
2006
ACM
14 years 1 months ago
Extensible control architectures
Architectural advances of modern systems has often been at odds with control complexity, requiring significant effort in both design and verification. This is particularly true ...
Greg Hoover, Forrest Brewer, Timothy Sherwood