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ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
14 years 4 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 11 months ago
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
Randal E. Bryant
PADS
1996
ACM
13 years 11 months ago
Conservative Circuit Simulation on Shared-Memory Multiprocessors
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
Jörg Keller, Thomas Rauber, Bernd Rederlechne...
IEICET
2007
75views more  IEICET 2007»
13 years 7 months ago
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits
We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation with noisy neural elements. Our aim is t...
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshi...
COMPLEXITY
2006
144views more  COMPLEXITY 2006»
13 years 7 months ago
BML revisited: Statistical physics, computer simulation, and probability
Statistical physics, computer simulation and discrete mathematics are intimately related through the study of shared lattice models. These models lie at the foundation of all thre...
Raissa M. D'Souza