This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
We investigate conservative parallel discrete event simulations for logical circuits on shared-memory multiprocessors. For a first estimation of the possible speedup, we extend th...
We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation with noisy neural elements. Our aim is t...
Statistical physics, computer simulation and discrete mathematics are intimately related through the study of shared lattice models. These models lie at the foundation of all thre...