246 search results - page 10 / 50 » Statistical gate sizing for timing yield optimization |
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
FPL
2009
Springer
14 years 5 days ago
2009
Springer
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
In nanometer regime, the effects of variations are having an increasing impact on the delay and power characteristics of devices as well as the yield of the circuit. Statistical t...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
- Power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. Disconnecting...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— Criticality and yield gradients are two crucial diagnostic metrics obtained from Statistical Static Timing Analysis (SSTA). They provide valuable information to guide timing op...