246 search results - page 19 / 50 » Statistical gate sizing for timing yield optimization |
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
EAAI
2010
13 years 6 months ago
2010
Aircraft sizing studies consist in determining the main characteristics of an aircraft starting from a set of requirements. These studies can be summarized as global constrained o...
ESAS
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. In this article we present the fastest known implementation of a modular multiplication for a 160-bit standard compliant elliptic curve (secp160r1) for 8-bit micro contro...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...