The purpose of this paper is to forecast the time evolution of a binary response variable from an associated continuous time series observed only at discrete time points that usual...
Ana M. Aguilera, Manuel Escabias, Mariano J. Valde...
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
On open and controversial issue in empirical data analysis is to decide whether scaling and multifractal properties observed in empirical data actually exist, or whether they are ...
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...