893 search results - page 16 / 179 » Statistical timing analysis using Kernel smoothing |
ISQED
2009
IEEE
14 years 4 months ago
2009
IEEE
A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. U...
PAA
2010
13 years 8 months ago
2010
By applying recent results in optimization theory variously known as optimization transfer or majorize/minimize algorithms, an algorithm for binary, kernel, Fisher discriminant ana...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
DAC
2004
ACM
14 years 11 months ago
2004
ACM
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
ICCAD
2003
IEEE
14 years 3 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...