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133
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FLAIRS
2007
15 years 6 months ago
2007
We describe an architecture for representing and managing context shifts that supports dynamic data interpretation. This architecture utilizes two layers of learning and three lay...
150
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ASPDAC
2008
ACM
15 years 6 months ago
2008
ACM
- With the increasing levels of variability in the behavior of manufactured nano-scale devices and dramatic changes in the power density on a chip, timely identification of hot spo...
136
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AAAI
1998
15 years 5 months ago
1998
This paperconsidersthe problem of representingcomplex systems that evolve stochastically over time. Dynamic Bayesian networks provide a compact representation for stochastic proce...
135
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ET
2002
15 years 3 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
151
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Presentation
Presented at First Electrical Science Divisional Symposium, Indian Institute of Science.
This is joint work with Prof David Parkes, Harvard University.