141 search results - page 19 / 29 » Strategies for dynamic memory allocation in hybrid architect... |
HPCA
2007
IEEE
14 years 2 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
Increasing demand for performance and efficiency has driven the computer industry toward multicore systems. These systems have become the industry standard in almost all segments...
ICCCN
2007
IEEE
14 years 2 months ago
2007
IEEE
—The emergence of multi-processor, multi-threaded architectures (referred to as multi- architectures) facilitates the design of high-throughput request processing systems (e.g., ...
IEEEPACT
2007
IEEE
14 years 1 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
IPPS
2009
IEEE
14 years 2 months ago
2009
IEEE
In the past few years, there has been a trend of providing increased computing power through greater number of cores on a chip, rather than through higher clock speeds. In order t...