697 search results - page 34 / 140 » Strategies to Parallelize ILP Systems |
RTSS
1999
IEEE
14 years 23 days ago
1999
IEEE
Packet switching in connection-oriented networks that may have multiple parallel links between pairs of switches is considered. An e cient packet-scheduling algorithm that guarant...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...
MICRO
2007
IEEE
14 years 2 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
SAMOS
2004
Springer
14 years 1 months ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
ISSS
2002
IEEE
14 years 1 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...