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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
RV
2009
Springer
155views Hardware» more  RV 2009»
14 years 4 days ago
Hardware Supported Flexible Monitoring: Early Results
Monitoring of software’s execution is crucial in numerous software development tasks. Current monitoring efforts generally require extensive instrumentation of the software or d...
Antonia Zhai, Guojin He, Mats Per Erik Heimdahl
DSRT
2008
IEEE
13 years 9 months ago
RTPROC: A System for Rapid Real-Time Prototyping in Audio Signal Processing
In this contribution a new system for the rapid development of real-time prototypes for digital audio signal processing algorithms on Windows PCs and a Digital Signal Processor (D...
Hauke Krüger, Peter Vary
3DPVT
2006
IEEE
233views Visualization» more  3DPVT 2006»
14 years 1 months ago
Scanline Optimization for Stereo on Graphics Hardware
In this work we propose a scanline optimization procedure for computational stereo using a linear smoothness cost model performed by programmable graphics hardware. The main idea ...
Christopher Zach, Mario Sormann, Konrad F. Karner
ISCA
2000
IEEE
92views Hardware» more  ISCA 2000»
14 years 4 hour ago
Trace preconstruction
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
Quinn Jacobson, James E. Smith