Sciweavers

871 search results - page 100 / 175
» Streaming Reduction Circuit
Sort
View
ICCD
1999
IEEE
91views Hardware» more  ICCD 1999»
14 years 2 months ago
Architectural Synthesis of Timed Asynchronous Systems
ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in...
Brandon M. Bachman, Hao Zheng, Chris J. Myers
FPGA
1997
ACM
168views FPGA» more  FPGA 1997»
14 years 2 months ago
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays
This paper shows that the speed of FPGAs with large embedded memory arrays can be improved by adding direct programmable connections between the memories. Nets that connect to mul...
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vran...
ISLPED
1995
ACM
113views Hardware» more  ISLPED 1995»
14 years 1 months ago
Low delay-power product CMOS design using one-hot residue coding
: CMOS implementations of arithmetic units for One-Hot Residue encoded operands are presented. They are shown to reduce the delay-power product of conventional, fully-encoded desig...
William A. Chren Jr.
ICMCS
2006
IEEE
162views Multimedia» more  ICMCS 2006»
14 years 4 months ago
Musical Signal Type Discrimination based on Large Open Feature Sets
Automatic discrimination of musical signal types as speech, singing, music, genres or drumbeats within audio streams is of great importance e.g. for radio broadcast stream segment...
Björn Schuller, Frank Wallhoff, Dejan Arsic, ...
VLDB
2004
ACM
103views Database» more  VLDB 2004»
14 years 3 months ago
Distributed Set Expression Cardinality Estimation
We consider the problem of estimating set-expression cardinality in a distributed streaming environment where rapid update streams originating at remote sites are continually tran...
Abhinandan Das, Sumit Ganguly, Minos N. Garofalaki...