871 search results - page 102 / 175 » Streaming Reduction Circuit |
GLVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
VTS
2006
IEEE
14 years 4 months ago
2006
IEEE
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
HICSS
2003
IEEE
14 years 3 months ago
2003
IEEE
Abstract— This paper presents a framework for verifying compilation tools for parametrised hardware libraries with placement information. Such libraries are captured in Pebble, a...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...