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ASPDAC
2009
ACM
184views Hardware» more  ASPDAC 2009»
14 years 2 months ago
FastRoute 4.0: global router with efficient via minimization
The number of vias generated during the global routing stage is a critical factor for the yield of final circuits. However, most global routers only approach the problem by chargin...
Yue Xu, Yanheng Zhang, Chris Chu
SAT
2010
Springer
141views Hardware» more  SAT 2010»
14 years 2 months ago
Synthesizing Shortest Linear Straight-Line Programs over GF(2) Using SAT
Non-trivial linear straight-line programs over the Galois field of two elements occur frequently in applications such as encryption or high-performance computing. Finding the shor...
Carsten Fuhs, Peter Schneider-Kamp
DFT
2004
IEEE
93views VLSI» more  DFT 2004»
14 years 2 months ago
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
FPL
2006
Springer
115views Hardware» more  FPL 2006»
14 years 1 months ago
A Congestion Driven Placement Algorithm for FPGA Synthesis
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
Yue Zhuo, Hao Li, Saraju P. Mohanty
EUROPAR
2000
Springer
14 years 1 months ago
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
We present a compiler algorithm called BitValue, which can discover both unused and constant bits in dusty-deck C programs. BitValue uses forward and backward dataflow analyses, ge...
Mihai Budiu, Majd Sakr, Kip Walker, Seth Copen Gol...