871 search results - page 20 / 175 » Streaming Reduction Circuit |
ISQED
2006
IEEE
14 years 3 months ago
2006
IEEE
— A methodology is proposed for interdependent setup time and hold time characterization of sequential circuits. Integrating the methodology into an industrial sign-off static ti...
APPROX
2008
Springer
13 years 12 months ago
2008
Springer
We consider (uniform) reductions from computing a function f to the task of distinguishing the output of some pseudorandom generator G from uniform. Impagliazzo and Wigderson [IW]...
FPGA
2010
ACM
14 years 6 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
ECCC
2010
13 years 10 months ago
2010
An errorless circuit for a boolean function is one that outputs the correct answer or "don't know" on each input (and never outputs the wrong answer). The goal of e...
ASPDAC
2005
ACM
14 years 3 months ago
2005
ACM
-We propose a method involvingselectivesignalgating to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current ...