871 search results - page 21 / 175 » Streaming Reduction Circuit |
ASPDAC
2000
ACM
14 years 2 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
FMCAD
2006
Springer
14 years 1 months ago
2006
Springer
We formally define--at the stream transformer level--a class of synchronous circuits that tolerate any variability in the latency of their environment. We study behavioral properti...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
In this paper, a wavelet based approach is proposed for the model order reduction of linear circuits in time domain. Compared with Chebyshev reduction method, the wavelet reductio...
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...