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ISCAS
2003
IEEE
131views Hardware» more  ISCAS 2003»
14 years 3 months ago
Process variation dimension reduction based on SVD
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
Zhuo Li, Xiang Lu, Weiping Shi
ICMCS
2006
IEEE
120views Multimedia» more  ICMCS 2006»
14 years 3 months ago
Video Encoding and Splicing for Tune-in Time Reduction in IP Datacasting (IPDC) Over DVB-H
A novel video encoding and splicing method is proposed which minimizes the tune-in time of “channel zapping”, i.e. changing from one audiovisual service to another, in IPDC ov...
Mehdi Rezaei, Miska M. Hannuksela, Moncef Gabbouj
IEEECIT
2010
IEEE
13 years 8 months ago
SAT: A Stream Architecture Template for Embedded Applications
- The increase of embedded applications complexity has demanded hardware more flexible while providing higher performance. Reconfigurable architectures and stream processing have b...
Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, ...
DAC
2005
ACM
14 years 11 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
ICCAD
2008
IEEE
109views Hardware» more  ICCAD 2008»
14 years 4 months ago
Transition-aware decoupling-capacitor allocation in power noise reduction
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
Po-Yuan Chen, Che-Yu Liu, TingTing Hwang