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ISPD
1998
ACM
244views Hardware» more  ISPD 1998»
14 years 2 months ago
Analysis, reduction and avoidance of crosstalk on VLSI chips
As chip size and design density increase, coupling effects (crosstalk) between signal wires become increasingly critical to on–chip timing and even functionality. A method is pr...
Tilmann Stöhr, Markus Alt, Asmus Hetzel, J&uu...
ISLPED
1997
ACM
116views Hardware» more  ISLPED 1997»
14 years 2 months ago
Power reduction techniques for a spread spectrum based correlator
This paper presents the design of a low power spread spectrum correlator. We look at two major approaches and evaluate the best alternative for power reduction. We first consider...
David Garrett, Mircea R. Stan
ET
2010
113views more  ET 2010»
13 years 7 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
ICAS
2005
IEEE
109views Robotics» more  ICAS 2005»
14 years 3 months ago
Proactive Route Maintenance and Overhead Reduction for Application Layer Multicast
— The purpose of this study is to maintain efficient backup routes for restoring overlay trees. In most conventional methods, after a node leaves the trees, its children start se...
Tetsuya Kusumoto, Yohei Kunichika, Jiro Katto, Sak...