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CEC
2005
IEEE
14 years 3 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
14 years 3 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
DATE
2003
IEEE
130views Hardware» more  DATE 2003»
14 years 3 months ago
Noise Macromodel for Radio Frequency Integrated Circuits
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
ISQED
2003
IEEE
73views Hardware» more  ISQED 2003»
14 years 3 months ago
A Novel Clocking Strategy for Dynamic Circuits
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
Young-Jun Lee, Jong-Jin Lim, Yong-Bin Kim
ENTCS
2011
77views more  ENTCS 2011»
13 years 5 months ago
Quantum Circuits: From a Network to a One-Way Model
Abstract—We present elements of quantum circuits translations from the (standard) network or circuit model to the one-way one. We present a translation scheme, give an account of...
Larisse Voufo