871 search results - page 6 / 175 » Streaming Reduction Circuit |
ISVLSI
2002
IEEE
14 years 2 months ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
— We develop a realizable circuit reduction to generate the interconnect macro-model for parasitic estimation in wideband applications. The inductance is represented by VPEC (vec...
ICCAD
2006
IEEE
14 years 6 months ago
2006
IEEE
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
ATVA
2004
Springer
14 years 3 months ago
2004
Springer
This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits effic...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
Input vector control (IVC) technique utilizes the stack effect in CMOS circuit to apply the minimum leakage vector (MLV) to the circuit at the sleep mode to reduce leakage. Additi...