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HPCA
2009
IEEE
14 years 9 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 2 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...
ASPLOS
2010
ACM
14 years 4 months ago
Virtualized and flexible ECC for main memory
We present a general scheme for virtualizing main memory errorcorrection mechanisms, which map redundant information needed to correct errors into the memory namespace itself. We ...
Doe Hyun Yoon, Mattan Erez
ICDE
2006
IEEE
206views Database» more  ICDE 2006»
14 years 10 months ago
Query Co-Processing on Commodity Hardware
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
Anastassia Ailamaki, Naga K. Govindaraju, Dinesh M...
COMCOM
2004
127views more  COMCOM 2004»
13 years 9 months ago
Traffic splitting in a network: split traffic models and applications
The contemporary high-speed networks, e.g. the Internet and asynchronous transfer mode (ATM) networks provide a convenient and cost-effective communication platform to carry the e...
Huei-Wen Ferng, Cheng-Ching Peng