2 search results - page 1 / 1 » Structure and Metrology for an Analog Testability Bus |
ITC
1993
IEEE
13 years 11 months ago
1993
IEEE
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic eects in an analog testability bus test environment. For the test response...