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» Structure-Preserving Model Reduction
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125
Voted
DAC
2002
ACM
16 years 3 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
139
Voted
DAC
2004
ACM
16 years 3 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
TACAS
2009
Springer
212views Algorithms» more  TACAS 2009»
15 years 9 months ago
Semantic Reduction of Thread Interleavings in Concurrent Programs
Abstract. We propose a static analysis framework for concurrent programs based on reduction of thread interleavings using sound invariants on the top of partial order techniques. S...
Vineet Kahlon, Sriram Sankaranarayanan, Aarti Gupt...
KBSE
2007
IEEE
15 years 9 months ago
Test suite reduction and prioritization with call trees
This paper presents a tool that (i) constructs tree-based models of a program’s behavior during testing and (ii) employs these trees while reordering and reducing a test suite. ...
Adam M. Smith, Joshua Geiger, Gregory M. Kapfhamme...
ISQED
2005
IEEE
78views Hardware» more  ISQED 2005»
15 years 8 months ago
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction
Abstract— To achieve small delay and low crosstalk for multiple signal nets with capacitive and inductive coupling, we propose in this paper a novel interconnect structure, stagg...
Hao Yu, Lei He