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MMB
2012
Springer
259views Communications» more  MMB 2012»
12 years 3 months ago
Boosting Design Space Explorations with Existing or Automatically Learned Knowledge
Abstract. During development, processor architectures can be tuned and configured by many different parameters. For benchmarking, automatic design space explorations (DSEs) with h...
Ralf Jahr, Horia Calborean, Lucian Vintan, Theo Un...
VISUALIZATION
1996
IEEE
13 years 11 months ago
Real-Time Incremental Visualization of Dynamic Ultrasound Volumes Using Parallel BSP Trees
We present a method for producing real-time volume visualizations of continuously captured, arbitrarily-oriented 2D arrays (slices) of data. Our system constructs a 3D representat...
William F. Garrett, Henry Fuchs, Mary C. Whitton, ...
ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
13 years 9 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
COMPGEOM
2006
ACM
13 years 11 months ago
I/O-efficient batched union-find and its applications to terrain analysis
Despite extensive study over the last four decades and numerous applications, no I/O-efficient algorithm is known for the union-find problem. In this paper we present an I/O-effic...
Pankaj K. Agarwal, Lars Arge, Ke Yi
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
14 years 2 months ago
Gate planning during placement for gated clock network
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu