Sciweavers

74 search results - page 11 / 15
» Supporting multithreading in configurable soft processor cor...
Sort
View
ISCA
2008
IEEE
148views Hardware» more  ISCA 2008»
14 years 2 months ago
Atomic Vector Operations on Chip Multiprocessors
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Y...
FPL
2010
Springer
155views Hardware» more  FPL 2010»
13 years 5 months ago
Design and Implementation of Real-Time Transactional Memory
Transactional memory is a promising, optimistic synchronization mechanism for chip-multiprocessor systems. The simplicity of atomic sections, instead of using explicit locks, is al...
Martin Schoeberl, Peter Hilber
FPL
2009
Springer
179views Hardware» more  FPL 2009»
13 years 11 months ago
Building heterogeneous reconfigurable systems using threads
Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...
Jason Agron, David L. Andrews
CGO
2009
IEEE
14 years 2 months ago
Computer Generation of General Size Linear Transform Libraries
The development of high-performance libraries has become extraordinarily difficult due to multiple processor cores, vector instruction sets, and deep memory hierarchies. Often, t...
Yevgen Voronenko, Frédéric de Mesmay...
ISCA
2012
IEEE
302views Hardware» more  ISCA 2012»
11 years 10 months ago
Scale-out processors
The emergence of global-scale online services has galvanized scale-out software, characterized by splitting vast datasets and massive computation across many independent servers. ...
Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, ...