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» SyCE: An Integrated Environment for System Design in SystemC
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FDL
2007
IEEE
14 years 1 months ago
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
The system description language SystemC enables to quickly create executable specifications at adequate levbstraction for both hardware/software integration and fast design space...
Daniel Große, Hernan Peraza, Wolfgang Klinga...
DDECS
2007
IEEE
139views Hardware» more  DDECS 2007»
14 years 1 months ago
Debug Patterns for Efficient High-level SystemC Debugging
This paper proposes debug patterns combined with an intuitive flow to accelerate and simplify the debugging of SystemC designs. A debug pattern provides a formalized procedure to f...
Frank Rogin, Erhard Fehlauer, Christian Haufe, Seb...
FDL
2005
IEEE
14 years 1 months ago
Embed Scripting inside SystemC
Embedded system designs and simulations become tedious and time consuming due to the complexity of modern applications. Thus, languages allowing high level description, such as Sy...
J. Vennin, S. Penain, Luc Charest, Samy Meftali, J...
CODES
2005
IEEE
14 years 1 months ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan
SIES
2008
IEEE
14 years 1 months ago
Scalably distributed SystemC simulation for embedded applications
SystemC becomes popular as an efficient system-level modelling language and simulation platform. However, the solethread simulation kernel obstacles its performance progress from ...
Kai Huang, Iuliana Bacivarov, Fabian Hugelshofer, ...