106 search results - page 7 / 22 » Symbolic Debugging Scheme for Optimized Hardware and Softwar... |
CAV
2012
Springer
11 years 11 months ago
2012
Springer
Abstract. We propose a trace-based concurrent program analysis to soundly remove redundant synchronizations such as locks while preserving the behaviors of the concurrent computati...
ASPDAC
2001
ACM
14 years 16 days ago
2001
ACM
Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance ...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
VTS
2002
IEEE
14 years 1 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
ICS
2007
Tsinghua U.
14 years 3 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...