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FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 9 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek
CODES
2005
IEEE
14 years 2 months ago
Dynamic phase analysis for cycle-close trace generation
For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system em...
Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh...
VTS
2006
IEEE
102views Hardware» more  VTS 2006»
14 years 2 months ago
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes
We consider self-testing of complete wireless nodes in the field through a low-energy software-based selftest (SBST) method. Energy consumption is optimized both for individual co...
Rong Zhang, Zeljko Zilic, Katarzyna Radecka
FMCAD
2007
Springer
14 years 3 months ago
Global Optimization of Compositional Systems
—Embedded systems typically consist of a composition of a set of hardware and software IP modules. Each module is heavily optimized by itself. However, when these modules are com...
Fadi A. Zaraket, John Pape, Adnan Aziz, Margarida ...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
14 years 2 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...