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DATE
2006
IEEE
114views Hardware» more  DATE 2006»
13 years 11 months ago
Compositional, efficient caches for a chip multi-processor
In current multi-media systems major parts of the functionality consist of software tasks executed on a set of concurrently operating processors. Those tasks interfere with each o...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
ICCD
2007
IEEE
182views Hardware» more  ICCD 2007»
14 years 2 months ago
Reducing leakage power in peripheral circuits of L2 caches
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
Houman Homayoun, Alexander V. Veidenbaum
HOTI
2005
IEEE
14 years 1 months ago
Hybrid Cache Architecture for High Speed Packet Processing
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
Zhen Liu, Kai Zheng, Bin Liu
JCP
2007
181views more  JCP 2007»
13 years 7 months ago
Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
Gürhan Küçük, Can Basaran
APCSAC
2003
IEEE
14 years 29 days ago
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main mem...
Philip Machanick, Zunaid Patel