96 search results - page 16 / 20 » Synapses as dynamic memory buffers |
TVCG
2010
13 years 5 months ago
2010
—We present a scheme for view-dependent level-of-detail control that is implemented entirely on programmable graphics hardware. Our scheme selectively refines and coarsens an ar...
ISPASS
2003
IEEE
13 years 12 months ago
2003
IEEE
Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism, and high computational requirements, making ...
JCST
2008
13 years 6 months ago
2008
Stride prefetching is recognized as an important technique to improve memory access performance. The prior work usually profiles and/or analyzes the program behavior offline, and u...
ASPLOS
2010
ACM
14 years 1 months ago
2010
ACM
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...