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DAC
1994
ACM
14 years 21 days ago
Clock Grouping: A Low Cost DFT Methodology for Delay Testing
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
Wen-Chang Fang, Sandeep K. Gupta
IJCNN
2006
IEEE
14 years 2 months ago
Complex Phase Synchronization in an Array of Oscillators Coupled by Time-Varying Resistor
— In recent years, many people have been trying to develop some applications to information processing by exploiting oscillatory phenomena in neural networks. Bifurcation and sta...
Yoko Uwate, Yoshifumi Nishio
ASPDAC
2001
ACM
81views Hardware» more  ASPDAC 2001»
14 years 7 days ago
High-level specification and efficient implementation of pipelined circuits
This paper describes a novel approach to high-level synthesis of complex pipelined circuits, including pipelined circuits with feedback. This approach combines a high-level, modula...
Maria-Cristina V. Marinescu, Martin C. Rinard
HPN
1994
13 years 10 months ago
Fast Connection Establishment in the DTM Gigabit Network
Dynamic synchronous Transfer Mode (DTM) is a new protocol suite based on synchronous fast circuit switching. The DTM network is based on bandwidth reservation and supports dynamic...
Per Lindgren, Christer Bohm
ISM
2006
IEEE
91views Multimedia» more  ISM 2006»
14 years 2 months ago
Real-Time Audio Watermarking System Prototype
A Real-Time audio watermarking system is presented. System contains two circuits: the marker circuit and the detector circuit. Watermark detection is blind, so, there is no necess...
Jose Juan Garcia Hernandez, Mariko Nakano-Miyatake...