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ISVLSI
2002
IEEE
129views VLSI» more  ISVLSI 2002»
14 years 1 months ago
Accelerating Retiming Under the Coupled-Edge Timing Model
Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz
DAC
2000
ACM
14 years 9 months ago
The use of carry-save representation in joint module selection and retiming
Joint module selection and retiming is a powerful technique to optimize the implementation cost and the speed of a circuit specified using a synchronous data-flow graph (DFG). In ...
Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
14 years 1 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
VLSID
1999
IEEE
87views VLSI» more  VLSID 1999»
14 years 27 days ago
Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized wh...
Vishwani D. Agrawal, Michael L. Bushnell, Ganapath...
BIRTHDAY
2003
Springer
14 years 1 months ago
Digital Algebra and Circuits
Abstract. Digital numbers D are the world’s most popular data representation: nearly all texts, sounds and images are coded somewhere in time and space by binary sequences. The m...
Jean Vuillemin