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JCIT
2010
111views more  JCIT 2010»
13 years 3 months ago
Shunt APF Based on Current Loop Repetitive Control
Three-phase shunt active power filter (APF) is often used to compensate the harmonic and reactive current derived from non-linear load. But many non-ideal factors, such as the lim...
Xueliang Wei
ICCD
1997
IEEE
158views Hardware» more  ICCD 1997»
14 years 3 days ago
Practical Advances in Asynchronous Design
Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practica...
Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
14 years 5 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
14 years 2 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 2 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni