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DATE
2003
IEEE
103views Hardware» more  DATE 2003»
14 years 2 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
ICC
2007
IEEE
229views Communications» more  ICC 2007»
14 years 1 months ago
A Cross-Layer Design on the Basis of Multiple Packet Reception in Asynchronous Wireless Network
This paper concerns the cross-layer design between physical layer and MAC (Multiple Access Control) layer in asynchronous wireless random access network. The proposed cross-layer d...
Anxin Li, Mingshu Wang, Xiangming Li, Hidetoshi Ka...
TON
1998
87views more  TON 1998»
13 years 8 months ago
Adaptive hybrid clock discipline algorithm for the network time protocol
This paper describes the analysis, implementation and performance of a new algorithm engineered to discipline a computer clock to a source of standard time, such as a GPS receiver...
David L. Mills
CPAIOR
2010
Springer
13 years 7 months ago
Boosting Set Constraint Propagation for Network Design
Abstract. This paper reconsiders the deployment of synchronous optical networks (SONET), an optimization problem naturally expressed in terms of set variables. Earlier approaches, ...
Justin Yip, Pascal Van Hentenryck, Carmen Gervet
ISVLSI
2008
IEEE
173views VLSI» more  ISVLSI 2008»
14 years 3 months ago
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
Julian J. H. Pontes, Matheus T. Moreira, Rafael So...