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SIGPLAN
2008
13 years 7 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
ISCAS
2003
IEEE
105views Hardware» more  ISCAS 2003»
14 years 22 days ago
Algorithmic partial analog-to-digital conversion in mixed-signal array processors
We present an algorithmic analog-to-digital converter (ADC) architecture for large-scale parallel quantization of internally analog variables in externally digital array processor...
Roman Genov, Gert Cauwenberghs
CODES
2002
IEEE
14 years 13 days ago
Design of multi-tasking coprocessor control for Eclipse
Eclipse defines a heterogeneous multiprocessor architecture template for data-dependent stream processing. Intended as a scalable and flexible subsystem of forthcoming media-proce...
Martijn J. Rutten, Jos T. J. van Eijndhoven, Evert...
DAC
1996
ACM
13 years 11 months ago
Symphony: A Simulation Backplane for Parallel Mixed-Mode Co-Simulation of VLSI Systems
In this paper we present an integrated simulation paradigm in which parallel mixed-mode co-simulation is accomplished by integrating sequential simulators in a software simulation ...
Antonio R. W. Todesco, Teresa H. Y. Meng
MICRO
1991
IEEE
115views Hardware» more  MICRO 1991»
13 years 11 months ago
Executing Loops on a Fine-Grained MIMD Architecture
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
Sunah Lee, Rajiv Gupta