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» Synchronous Interlocked Pipelines
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DAC
1994
ACM
13 years 11 months ago
Automatic Verification of Pipelined Microprocessors
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
Vishal Bhagwati, Srinivas Devadas
ICCAD
2004
IEEE
87views Hardware» more  ICCAD 2004»
14 years 4 months ago
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
V. Seth, Min Zhao, Jiang Hu
ARVLSI
1999
IEEE
112views VLSI» more  ARVLSI 1999»
13 years 11 months ago
Architectural Considerations for Application-Specific Counterflow Pipelines
Application-specific processor design is a promising approach for meeting the performance and cost goals of a system. Application-specific processors are especially promising for ...
Bruce R. Childers, Jack W. Davidson
DAC
2007
ACM
14 years 8 months ago
Self-Resetting Latches for Asynchronous Micro-Pipelines
Asynchronous circuits are increasingly attractive as low power or high-performance replacements to synchronous designs. A key part of these circuits are asynchronous micropipeline...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
FCCM
2005
IEEE
142views VLSI» more  FCCM 2005»
14 years 1 months ago
FPGA-Based Vector Processing for Solving Sparse Sets of Equations
The solution to a set of sparse linear equations Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained using the W-matrix method. An enhanced vect...
Muhammad Z. Hasan, Sotirios G. Ziavras