171 search results - page 11 / 35 » Synthesis of Efficient Linear Test Pattern Generators |
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
AAAI
2010
13 years 9 months ago
2010
The goal of testing is to discriminate between multiple hypotheses about a system--for example, different fault diagnoses--by applying input patterns and verifying or falsifying t...
VLSID
2005
IEEE
14 years 9 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
MTDT
2000
IEEE
14 years 1 months ago
2000
IEEE
In this work, we present the application of Generalized Linear Feedback Shift Registers (GLFSRs) for generation of patterns for pseudo-random memory Built-In SelfTest (BIST). Rece...
ASE
2010
13 years 9 months ago
2010
Recent developments in runtime verification and monitoring show that parametric regular and temporal logic specifications can be efficiently monitored against large programs. Howev...