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» Synthesis of Fault-Tolerant Distributed Systems
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118
Voted
ISCA
2009
IEEE
137views Hardware» more  ISCA 2009»
15 years 10 months ago
A case for an interleaving constrained shared-memory multi-processor
Shared-memory multi-threaded programming is inherently more difficult than single-threaded programming. The main source of complexity is that, the threads of an application can in...
Jie Yu, Satish Narayanasamy
132
Voted
ISLPED
2004
ACM
139views Hardware» more  ISLPED 2004»
15 years 8 months ago
Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
Kim M. Hazelwood, David Brooks
150
Voted
EDCC
2008
Springer
15 years 5 months ago
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satis...
Roman Obermaisser, Hubert Kraut, Christian El Sall...
CONEXT
2009
ACM
15 years 4 months ago
Virtually eliminating router bugs
Software bugs in routers lead to network outages, security vulnerabilities, and other unexpected behavior. Rather than simply crashing the router, bugs can violate protocol semant...
Eric Keller, Minlan Yu, Matthew Caesar, Jennifer R...
ATAL
2004
Springer
15 years 8 months ago
Multiagent Planning as Control Synthesis
This paper proposes a new multiagent planning approach to coordination synthesis that views distributed agents as discrete-event processes. The connection between discreteevent co...
Kiam Tian Seow, Chuan Ma, Makoto Yokoo