80 search results - page 13 / 16 » Synthesis of Optimal Interfaces for Hierarchical Scheduling ... |
DAC
1995
ACM
13 years 11 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
DATE
2010
IEEE
14 years 17 days ago
2010
IEEE
—As Electronic Control Units (ECUs) and embedded software functions within an automobile keep increasing in number, the scale and complexity of automotive embedded systems is gro...
GROUP
2005
ACM
14 years 1 months ago
2005
ACM
Recent proliferation of computing devices has brought attention to heterogeneous collaborative systems, where key challenges arise from the resource limitations and disparities. S...