80 search results - page 5 / 16 » Synthesis of Optimal Interfaces for Hierarchical Scheduling ... |
ICCAD
2000
IEEE
14 years 1 months ago
2000
IEEE
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—High computational effort in modern image processing applications like medical imaging or high-resolution video processing often demands for massively parallel special p...
EMSOFT
2001
Springer
14 years 1 months ago
2001
Springer
Abstract. Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting...
ISSS
2002
IEEE
14 years 1 months ago
2002
IEEE
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...