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VTS
1995
IEEE
94views Hardware» more  VTS 1995»
13 years 11 months ago
Synthesis of locally exhaustive test pattern generators
Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compu...
Günter Kemnitz
ICCD
2002
IEEE
152views Hardware» more  ICCD 2002»
14 years 4 months ago
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors
A circuit or circuit component that does not contain any spurious switching activity, i.e., activity that is not required by its specified functionality, is called perfectly power...
Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha
DAC
1998
ACM
14 years 8 months ago
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test ci...
Alexander Grießing, Paolo Ienne
ICCD
2002
IEEE
101views Hardware» more  ICCD 2002»
14 years 4 months ago
Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering
Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Popular repre...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
ICCAD
2001
IEEE
97views Hardware» more  ICCAD 2001»
14 years 4 months ago
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiova...